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1 LTC1668 16-bit, 50msps dac february 2000 n 50msps update rate n 16-bit resolution n high spectral purity: 87db sfdr at 1mhz f out n differential current outputs n 30ns settling time n 5pv-s glitch impulse n low power: 180mw from 5v supplies n ttl/cmos (3.3v or 5v) inputs n small package: 28-pin ssop the ltc ? 1668 is a 16-bit, 50msps differential current output dac implemented on a high performance bicmos process with laser trimmed, thin-film resistors. the com- bination of a novel current-steering architecture and a high performance process produces a dac with excep- tional ac and dc performance. this is the first 16-bit dac in the marketplace to exhibit an sfdr (spurious free dynamic range) of 87db for an output signal frequency of 1mhz. operating from 5v supplies, the LTC1668 can be con- figured to provide full-scale output currents up to 10ma. the differential current outputs of the dac allow single- ended or true differential operation. the C1v to 1v output compliance of the LTC1668 allows the outputs to be con- nected directly to external resistors to produce a differ- ential output voltage without degrading the converters linearity. alternatively, the outputs can be connected to the summing junction of a high speed operational amplifier, or to a transformer. the LTC1668 is available in a 28-pin ssop and is fully specified over the industrial temperature range. , ltc and lt are registered trademarks of linear technology corporation. n cellular base stations n multicarrier base stations n wireless communication n direct digital synthesis (dds) n xdsl modems n arbitrary waveform generation n automated test equipment n instrumentation 16-bit, 50msps dac final electrical specifications information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. + 16-bit high speed dac 2.5v reference v ss v dd ?v clock input 16-bit data input ladcom agnd dgnd clk db15 db0 1668 ta01 i out a 0.1 f LTC1668 5v 52.3 i refin refout comp1 comp2 c2 0.1 f 0.1 f c1 0.1 f r set 2k i out b 52.3 v out 1v p-p differential + 0.1 f frequency (1.25mhz/div) 0.05 signal amplitude (dbm) ?5 ?5 ? 1668 g01 ?5 ?5 ?5 ?5 ?5 ?5 ?5 ?05 6.3 12.55 f clock = 25msps f out = 1.007mhz amplitude = 0dbfs = 8.5dbm sfdr = 86dbc single tone sfdr features descriptio u applicatio s u typical applicatio u
2 LTC1668 LTC1668cg LTC1668ig t jmax = 110 c, q ja = 100 c/w order part number consult factory for military grade parts. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) db14 db15 (msb) clk v dd dgnd v ss comp2 comp1 i out a i out b ladcom agnd i refin refout the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 5v, v ss = C 5v, ladcom = agnd = dgnd = 0v, i outfs = 10ma. (note 1) supply voltage (v dd ) ................................................ 6v negative supply voltage (v ss ) ............................... C 6v total supply voltage (v dd to v ss ) .......................... 12v digital input voltage .................... C 0.3v to (v dd + 0.3v) analog output voltage (i out a and i out b ) ........ (v ss C 0.3v) to (v dd + 0.3v) power dissipation ............................................. 500mw operating temperature range LTC1668c .............................................. 0 c to 70 c LTC1668i ........................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c symbol parameter conditions min typ max units dc accuracy (measured at i outa , driving a virtual ground) resolution 16 bits monotonicity 14 bits inl integral nonlinearity 8 lsb dnl differential nonlinearity 1 4 lsb offset error 0.1 0.2 % fsr offset error drift 5 ppm/ c ge gain error internal reference, r irefin = 2k 2 % fsr external reference, v ref = 2.5v, r irefin = 2k 1 % fsr gain error drift internal reference 75 ppm/ c external reference 50 ppm/ c psrr power supply rejection ratio v dd = 5v 5% 0.1 % fsr/v v ss = C5v 5% 0.1 % fsr/v analog output i outfs full-scale output current l 110ma output compliance range i fs = 10ma l C1 1 v output resistance; r iouta , r ioutb i outa, b to ladcom l 0.7 1.1 1.5 k w output capacitance 5pf reference output reference voltage refout tied to i refin through 2k w 2.475 2.5 2.525 v reference output drift 25 ppm/ c reference output load regulation i load = 0ma to 5ma 6 mv/ma package/order i for atio uu w absolute axi u rati gs w ww u electrical characteristics
3 LTC1668 the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 5v, v ss = C 5v, ladcom = agnd = dgnd = 0v, i outfs = 10ma. note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. electrical characteristics symbol parameter conditions min typ max units reference input reference small-signal bandwidth i fs = 10ma, c comp1 = 0.1 m f20khz power supply v dd positive supply voltage l 4.75 5 5.25 v v ss negative supply voltage l C 4.75 C 5 C 5.25 v i dd positive supply current i fs = 10ma, f clk = 25msps, f out = 1mhz l 35 ma i ss negative supply current i fs = 10ma, f clk = 25msps, f out = 1mhz l 33 40 ma p dis power dissipation i fs = 10ma, f clk = 25msps, f out = 1mhz l 180 mw i fs = 1ma, f clk = 25msps, f out = 1mhz l 85 mw dynamic performance (differential transformer coupled output, 50 w double terminated, unless otherwise noted) f clock maximum update rate l 50 75 msps t s output settling time to 0.1% fsr 30 ns t pd output propagation delay 8ns glitch impulse single ended 15 pv-s differential 5 pv-s t r output rise time 4ns t f output fall time 4ns i no output noise i fs = 10ma 50 pa/ ? hz i fs = 1ma 30 pa/ ? hz ac linearity sfdr spurious free dynamic range f clk = 25msps, f out = 1mhz to nyquist 0db fs output 78 87 db C 6db fs output 87 db C12db fs output 86 db C18db fs output 80 db f clk = 50msps, f out = 1mhz 84 db f clk = 50msps, f out = 2.5mhz 80 db f clk = 50msps, f out = 5mhz 77 db f clk = 50msps, f out = 20mhz 65 db spurious free dynamic range f clk = 25msps, f out = 1mhz, 2mhz span 86 96 db within a window f clk = 50msps, f out = 5mhz, 4mhz span 88 db thd total harmonic distortion f clk = 25msps, f out = 1mhz C84 C77 db f clk = 50msps, f out = 5mhz C76 db digital inputs v ih digital high input voltage l 2.4 v v il digital low input voltage l 0.8 v i in digital input current l 10 m a c in digital input capacitance 5pf t ds input setup time l 8ns t dh input hold time l 4ns t clkh clock high time l 5ns t clkl clock low time l 8ns
4 LTC1668 typical perfor a ce characteristics uw frequency (1.25mhz/div) 0.05 signal amplitude (dbm) ?5 ?5 ? 1668 g01 ?5 ?5 ?5 ?5 ?5 ?5 ?5 ?05 6.3 12.55 f clock = 25msps f out = 1.007mhz amplitude = 0dbfs = 8.5dbm sfdr = 86dbc single tone sfdr 2-tone sfdr frequency (0.2mhz/div) 3.2 signal amplitude (dbm) ?0 ?0 ?0 1668 g02 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 4.2 5.2 f clock = 50msps f out1 = 4.028mhz f out2 = 4.419mhz amplitude 1, 2 = 6dbfs = 14.5dbm sfdr > 77dbc integral nonlinearity differential nonlinearity digital input code ? integral nonlinearity (lsb) ? ? ? 0 5 2 16384 32768 1668 g03 ? 3 4 1 49152 65535 digital input code 0 differential nonlinearity (lsb) 0 1.0 65535 1668 g04 ?.0 2.0 16384 32768 49152 2.0 0.5 0.5 ?.5 1.5 uu u pi fu ctio s refout (pin 15): internal reference voltage output. nominal value is 2.5v. requires a 0.1 m f bypass capacitor to agnd. i refin (pin 16): reference input current. nominal value is 1.25ma for i fs = 10ma. i fs = i refin ? 8. agnd (pin 17): analog ground. ladcom (pin 18): attenuator ladder common. normally tied to gnd. i out b (pin 19): complementary dac output current. full- scale output current occurs when all data bits are 0s. i out a (pin 20): dac output current. full-scale output current occurs when all data bits are 1s. comp1 (pin 21): current source control amplifier com- pensation. bypass to v ss with 0.1 m f. comp2 (pin 22): internal bypass point. bypass to v ss with 0.1 m f. v ss (pin 23): negative supply voltage. nominal value is C 5v. dgnd (pin 24): digital ground. v dd (pin 25): positive supply voltage. nominal value is 5v. clk (pin 26): clock input. data is latched and the output is updated on positive edge of clock. db15 to db0 (pins 27, 28, 1 to 14): digital input data bits.
5 LTC1668 block diagra w + i fs /8 irefin i int r set 2k 0.1 f 0.1 f 0.1 f ?v 0.1 f refout v ref LTC1668 15 16 comp1 21 comp2 v ss 22 23 2.5v reference attenuator ladder lsb switches input latches clock input 16-bit data input segmented switches for db15?b12 current source array agnd 17 dgnd 24 clk db0 db15 ?? ?? ? 26 27 14 1668 bd 18 ladcom 20 i out a 19 i out b 52.3 52.3 v out 1v p-p differential + 0.1 f 25 5v ti i g diagra u ww 1668 td t ds t dh clk n ?1 n ?1 n n n + 1 db0 to db15 i out a /i out b t clkl t clkh t pd 0.1% t st
6 LTC1668 applicatio s i for atio wu uu theory of operation the LTC1668 is a high speed current steering 16-bit dac made on an advanced bicmos process. precision thin film resistors and well matched bipolar transistors result in excellent dc linearity and stability. a low glitch current switching design gives excellent ac performance at sample rates up to 50msps. the device is complete with a 2.5v internal bandgap reference and edge triggered latches, and sets a new standard for dac applications requiring very high dynamic range at output frequencies up to several megahertz. referring to the block diagram, the dac contains an array of current sources that are steered to i outa or i outb with nmos differential current switches. the four most signifi- cant bits, db15 to db12 are made up of 15 current segments of equal weight. the lower bits, db11 to db0 are binary weighted, using a combination of current scaling and a differential resistive attenuator ladder. all bits and segments are precisely matched, both in current weight for dc linearity, and in switch timing for low glitch impulse and low spurious tone ac performance. setting the full-scale current, i outfs the full-scale dac output current, i outfs , is nominally 10ma, and can be adjusted down to 1ma. placing a resistor, r set , between the refout pin, and the i refin pin sets i outfs as follows. the internal reference control loop amplifier maintains a virtual ground at i refin by servoing the internal current source, i int , to sink the exact current flowing into i refin . i int is a scaled replica of the dac current sources and i outfs = 8 ? (i int ), therefore: i outfs = 8 ? (i refin ) = 8 ? (v ref /r set ) (1) for example, if r set = 2k and is tied to v ref = refout = 2.5v, i refin = 2.5/2k = 1.25ma and i outfs = 8 ? (1.25ma) = 10ma. the reference control loop requires a capacitor on the comp1 pin for compensation. for optimal ac perfor- mance, c comp1 should be connected to v ss and be placed very close to the package (less than 0.1"). for fixed reference voltage applications, c comp1 should be 0.1 m f or more. the reference control loop small-signal bandwidth is approximately 1/(2 p ) ? c comp1 ? 80 or 20khz for c comp1 = 0.1 m f. internal reference outputrefout the onboard 2.5v bandgap voltage reference drives the refout pin. it is trimmed and specified to drive a 2k resistor tied from refout to i refin , corresponding to a 1.25ma load (i outfs = 10ma). refout has nominal output impedance of 6 w , or 0.24% per ma, so it must be buffered to drive any additional external load. a 0.1 m f capacitor is required on the refout pin for compensa- tion. note that this capacitor is required for stability, even if the internal reference is not being used. dac transfer function the LTC1668 uses straight binary digital coding. the complementary current outputs, i out a and i out b , sink current from 0 to i outfs . for i outfs = 10ma (nominal), i out a swings from 0ma when all bits are low (i.e., code = 0) to 10ma when all bits are high (i.e., code = 65535) (deci- mal representation). i out b is complementary to i out a . i out a and i out b are given by the following formulas: i out a = i outfs ? (dac code/65536) (2) i out b = i outfs ? (65535-dac code)/65536 (3) in typical applications, the LTC1668 differential output currents either drive a resistive load directly or drive an equivalent resistive load through a transformer, or as the feedback resistor of an i-to-v converter. the voltage outputs generated by the i out a and i out b output currents are then: v out a = i out a ? r load (4) v out b = i out b ? r load (5) the differential voltage is: v diff = v out a C v out b (6) = (i out a C i out b ) ? (r load )
7 LTC1668 applicatio s i for atio wu uu substituting the values found earlier for i out a , i out b and i outfs : v diff = {2 ? dac code C 65535)/65536} ? 8 ? (r load /r set ) ? (v ref ) (7) from these equations some of the advantages of differen- tial mode operation can be seen. first, any common mode noise or error on i out a and i out b is cancelled. second, the signal power is twice as large as in the single-ended case. third, any errors and noise that multiply times i out a and i out b , such as reference or i outfs noise, cancel near midscale, where ac signal waveforms tend to spend the most time. fourth, this transfer function is bipolar; e.g. the output swings positive and negative around a zero output at mid-scale input, which is more convenient for ac applications. note that the term (r load /r set ) appears in both the differential and single-ended transfer functions. this means that the gain error of the dac depends on the ratio of r load to r set , and the gain error tempco is affected by the temperature tracking of r load with r set . note also that the absolute tempco of r load is very critical for dc nonlinearity. as the dac output changes from 0ma to 10ma the r load resistor will heat up slightly, and even a very low tempco can produce enough inl bowing to be significant at the 16-bit level. this effect disappears with medium to high frequency ac signals due to the slow thermal time constant of the load resistor. analog outputs the LTC1668 has two complementary current outputs, i out a and i out b (see dac transfer function). the output impedance of i out a and i out b (r iout a and r iout b ) is typically 1.1k w to ladcom. (see the equivalent analog output circuit, figure 1.) the ladcom pin is the com- mon connection for the internal dac attenuator ladder. it usually is tied to analog ground, but more generally it should connect to the same potential as the lead resistors on i out a and i out b . the ladcom pin carries a constant current to v ss of approximately 0.32 ? (i outfs ), plus any current that flows from i out a and i out b through the r iout a and r iout b resistors. the specified output compliance voltage range is 1v. the dc linearity specifications, inl and dnl, are trimmed and guaranteed on i out a into the virtual ground of an i-to-v converter, but are typically very good over the full output compliance range. above 1v the output current will start to increase as the dac current steering switch impedance decreases, degrading both dc and ac linear- ity. below C 1v, the dac switches will start to approach the transition from saturation to linear region. this will de- grade ac performance first, due to nonlinear capacitance and increased glitch impulse. ac distortion performance is optimal at amplitudes less than 0.5v p-p on i out a and i out b due to nonlinear capacitance and other large-signal effects. at first glance, it may seem counter-intuitive to decrease the signal amplitude when trying to optimize sfdr. however, the error sources that affect ac perfor- mance generally behave as additive currents, so decreas- ing the load impedance to reduce signal voltage amplitude will reduce most spurious signals by the same amount. the LTC1668 is specified to operate with full-scale output current, i outfs , from the nominal 10ma down to 1ma. this can be useful to reduce power dissipation or to adjust full-scale value. however, that the LTC1668 dc and ac accuracy is specified only at i outfs = 10ma, and dc and ac accuracy will fall off significantly at lower i outfs values. at i outfs = 1ma, inl and dnl typically degrade to the 14- bit to 13-bit level, compared to 16-bit to 15-bit typical accuracy at 10ma i outfs . increasing i outfs from 1ma, the 20 19 23 18 r iout b 1.1k 5pf LTC1668 5pf ?v 1668 f01 r iout a 1.1k ladcom i out a i out b v ss 52.3 52.3 figure 1. equivalent analog output circuit
8 LTC1668 applicatio s i for atio wu uu accuracy improves rapidly, roughly in proportion to 1/i outfs . the ac performance tends to be less affected by reducing i outfs , except for the unavoidable affects on sfdr and thd due to increased inl and dnl. output configurations based on the specific application requirements, the LTC1668 allows a choice of the best of several output configurations. voltage outputs can be generated by ex- ternal load resistors, transformer coupling or with an op amp i-to-v converter. single-ended dac output configu- rations use only one of the outputs, preferably i out a , to produce a single-ended voltage output. differential mode configurations use the difference between i out a and i out b to generate an output voltage, v diff , as shown in equation 7. differential mode gives much better accuracy in most ac applications. because the dac chip is the point of interface between the digital input signals and the analog output, some small amount of noise coupling to i out a and i out b is unavoidable. most of that digital noise is common mode and is canceled by the differential mode circuit. other significant digital noise components can be modeled as v ref or i outfs noise. in single-ended mode, i outfs noise is gone at zero scale and is fully present at full scale. in differential mode, i outfs noise is cancelled at midscale input, corresponding to zero analog output. many ac signals, including broadband and multitone communications signals with high peak to average ratios, stay mostly near midscale. differential transformer-coupled output configurations usually give the best ac performance. an example is the ac characterization setup circuit, figure 2. the advan- tages of transformer coupling include excellent rejection of common mode distortion and noise over a broad frequency range and convenient differential-to-single- ended conversion with isolation or level shifting. also, as much as twice the power can be delivered to the load, and impedance matching can be accomplished by selecting the appropriate transformer turns ratio. the center tap on the primary side of the transformer is tied to ground to provide the dc current path for i out a and i out b . for low distortion, the dc average of the i out a and i out b currents must be exactly equal to avoid biasing the core. this is especially important for compact rf transformers with small cores. the circuit in figure 2 uses a mini-circuits t1-1t rf transformer with a 1:1 turns ratio. the load + 16-bit high speed dac hp1663ea logic analyzer with pattern generator 2.5v reference v ss v dd ?v ladcom agnd dgnd clk db15 db0 16 digital data clk in 1668 f02 i out a 0.1 f LTC1668 5v i refin refout comp1 comp2 c2 0.1 f 0.1 f out 1 out 2 c1 0.1 f r set 2k i out b hp8110a dual pulse generator low jitter clock source clk in 50 0.1 f 50 to hp3589a spectrum analyzer 50 input 110 mini-circuits t1?t figure 2. ac characterization setup
9 LTC1668 applicatio s i for atio wu uu resistance on i out a and i out b is equivalent to a single differential resistor of 50 w , and the 1:1 turns ratio means the output impedance from the transformer is 50 w . note that the load resistors are optional, and they dissipate half of the output power. however, in lab environments or when driving long transmission lines it is very desirable to have a 50 w output impedance. this could also be done with a 50 w resistor at the transformer secondary, but putting the load resistors on i out a and i out b is preferred since it reduces the current through the transformer. at signal frequencies lower than about 1mhz, the trans- former core size required to maintain low distortion gets larger, and at some lower frequencies this becomes impractical. a differential resistor loaded output configuration is shown in the block diagram. it is simple and economical, but it can drive only differential loads with impedance levels and amplitudes appropriate for the dac outputs. the recommended single-ended resistor loaded configu- ration is essentially the same circuit as the differential resistor loaded, casesimply use the i out a output, referred to ground. rather than tying the unused i out b output to ground, it is preferred to load it with the equiva- lent r load of i out a . then i out b will still swing with a waveform complementary to i out a . adding an op amp differential to single-ended converter circuit to the differential resistor loaded output gives the circuit of figure 10. this circuit complements the capabilities of the trans- former-coupled application at lower frequencies, since available op amps can deliver good ac distortion perfor- mance at signal frequencies of a few mhz down to dc. the optional capacitor adds a single real pole of filtering, and helps reduce distortion by limiting the high frequency signal amplitude at the op amp inputs. the circuit swings 1v around ground. figure 3 shows a simplified circuit for a single-ended output using i-to-v converter to produce a unipolar buffered voltage output. this configuration typically has the best dc linearity performance, but its ac distortion at higher frequencies is limited by u1s slewing capabilities. 200 1668 f03 i out a i out b ladcom LTC1668 r fb 200 v out 0v to 2v i outfs 10ma c out + u1 lt 1812 figure 3. unipolar buffered voltage output digital interface the LTC1668 has 16 parallel inputs that are latched on the rising edge of the clock input. they accept cmos levels from either 5v or 3.3v logic and can accept clock rates of up to 50mhz. referring to the timing diagram and block diagram, the data inputs go to master-slave latches that update on the rising edge of the clock. the input logic thresholds, v ih = 2.4v min, v il = 0.8v max, work with 3.3v or 5v cmos levels over temperature. the guaranteed setup time, t ds , is 8ns minimum and the hold time, t dh , is 4ns minimum. the minimum clock high and low times are guaranteed at 6ns and 8ns, respectively. these specifications allow the LTC1668 to be clocked at up to 50msps minimum. for best ac performance, the data and clock waveforms need to be clean and free of undershoot and overshoot. clock and data interconnect lines should be twisted pair, coax or microstrip, and proper line termination is impor- tant. if the digital input signals to the dac are considered as analog ac voltage signals, they are rich in spectral components over a broad frequency range, usually in- cluding the output signal band of interest. therefore, any direct coupling of the digital signals to the analog output will produce spurious tones that vary with the exact digital input pattern. clock jitter should be minimized to avoid degrading the noise floor of the device in ac applications, especially where high output frequencies are being generated. any noise coupling from the digital inputs to the clock input will
10 LTC1668 applicatio s i for atio wu uu cause phase modulation of the clock signal and the dac waveform, and can produce spurious tones. it is normally best to place the digital data transitions near the falling clock edge, well away from the active rising clock edge. because the clock signal contains spectral components only at the sampling frequency and its multiples, it is usually not a source of in band spurious tones. overall, it is better to treat the clock as you would an analog signal and route it separately from the digital data input signals. the clock trace should be routed either over the analog ground plane or over its own section of the ground plane. the clock line needs to have accurately controlled imped- ance and should be well terminated near the LTC1668. printed circuit board layout considerations grounding, bypassing and output signal routing the close proximity of high frequency digital data lines and high dynamic range, wide-band analog signals makes clean printed circuit board design and layout an absolute necessity. figures 5 to 9 are the printed circuit board layers for an ac evaluation circuit for the LTC1668. ground planes should be split between digital and analog sections as shown. all bypass capacitors should have minimum trace length and be ceramic 0.1 m f or larger with low esr. bypass capacitors are required on v ss , v dd and refout, and all connected to the agnd plane. the comp2 pin ties to a node in the output current switching circuitry, and it requires a 0.1 m f bypass capacitor. it should be bypassed to v ss along with comp1. the agnd and dgnd pins should both tie directly to the agnd plane, and the tie point between the agnd and dgnd planes should nominally be near the dgnd pin. ladcom should either be tied directly to the agnd plane or be bypassed to agnd. the i out a and i out b traces should be close together, short, and well matched for good ac cmrr. the transformer output ground should be capable of optionally being isolated or being tied to the agnd plane, depending on which gives better performance in the system. suggested evaluation circuit figure 4 is the schematic and figures 5 to 9 are the circuit board layouts for a suggested evaluation circuit, dc245a. the circuit can be programmed with component selection and jumpers for a variety of differentially coupled trans- former output and differential and single-ended resistor loaded output configurations.
11 LTC1668 applicatio s i for atio wu uu figure 4. suggested evaluation circuit j4 v out j5 i out b j6 extclk jp9 123 15 16 r3 1.91k 0.1% r2 200 jp1 c17 0.1 f LTC1668-28 20 19 21 22 23 18 c7 0.1 f 5v ?v tp5 testpoint wht c3 0.1 f c18 0.1 f 25 17 24 c10 0.1 f c11 0.1 f r9 50 0.1% r12 49.9 1% jp6 r10 50 0.1% c12 22pf c12 22pf c9 0.1 f c8 0.1 f c8 0.1 f jp5 tp3 testpoint wht jp7 jp3 r5 r6 r7 110 jp4 jp2 5v refout refin 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 26 db15 (msb) db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 clk 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 i out a i out b comp1 comp2 v ss ladcom v dd agnd dgnd r4 j2 i out a c4 r8 3 2 1 4 t1 mini- circuits t1?t 6 c5 jp8 tp4 testpoint wht 2 4 6 1 3 5 rn5 +5vd 22 +5vd j7 j10 tp6 testpoint red 4 2 5v 6 lt1460dcs8-2.5 amp 102159-9 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 rn6 22 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 tp2 testpoint wht 2.5v ref tp10 testpoint blk tp1 v in v out gnd c2 0.1 f c1 0.1 f j1 extref r1 10 + c19 0.1 f c14 10 f 25v ?v agnd dgnd j9 tp8 testpoint red ground plane tie point + c20 0.1 f c16 10 f 25v 1668 f04 c22 0.1 f +5va j8 j11 tp7 testpoint red tp9 testpoint blk + c23 0.1 f c15 10 f 25v c21 0.1 f optional sip pull-up/ pull-down resistors (not installed) optional sip pull-up/ pull-down resistors (not installed) +5vd
12 LTC1668 applicatio s i for atio wu uu figure 5. suggested evaluation circuit boardsilkscreen figure 6. suggested evaluation circuit boardcomponent side
13 LTC1668 applicatio s i for atio wu uu figure 7. suggested evaluation circuit boardgnd plane figure 8. suggested evaluation circuit boardpower plane
14 LTC1668 applicatio s i for atio wu uu figure 9. suggested evaluation circuit boardsolder side
15 LTC1668 dimensions in millimeters (inches) unless otherwise noted. g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) u package descriptio g28 ssop 1098 0.13 ?0.22 (0.005 ?0.009) 0 ?8 0.55 ?0.95 (0.022 ?0.037) 5.20 ?5.38** (0.205 ?0.212) 7.65 ?7.90 (0.301 ?0.311) 1234 5 6 7 8 9 10 11 12 14 13 10.07 ?10.33* (0.397 ?0.407) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 1.73 ?1.99 (0.068 ?0.078) 0.05 ?0.21 (0.002 ?0.008) 0.65 (0.0256) bsc 0.25 ?0.38 (0.010 ?0.015) note: dimensions are in millimeters dimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * **
16 LTC1668 ? linear technology corporation 2000 1668i lt/tp 0200 4k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com part number description comments ltc1406 8-bit, 20msps adc undersampling capability up to 70mhz input ltc1414 14-bit, 2.2msps adc 84db sfdr at 1.1mhz f in ltc1420 12-bit, 10msps adc 72db sinad at 5mhz f in ltc1604 16-bit, 333ksps adc 16-bit, no missing codes, 90db sinad, C100db thd related parts typical applicatio u figure 10. high speed buffered v out dac + 16-bit high speed dac 2.5v reference v ss v dd ?v clock input 16-bit data input ladcom agnd dgnd clk db15 db0 1668 f10 i out a 0.1 f LTC1668 5v i refin refout comp1 comp2 0.1 f 0.1 f 0.1 f r set 2k i out b 0.1 f + 500 500 v out 1v 10dbm lt 1812 200 200 c opt 52.3 52.3

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